FPGA/RTLJan 2024
Hardware Accelerator for Vision Transformer-based Malware Detection
DVCon India 2024 Design Contest - ViT-based malware detection on RISC-V edge devices
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About This Project
This project aims to deploy a ViT-based malware detection system on an edge device equipped with the VEGA AS1061 Processor.
Stage 1 focuses on proposing a novel acceleration IP to enhance the ViT model's inference performance on the VEGA Processor, ensuring effective malware detection in real-world scenarios.
Competed at DVCon India 2024 Design Contest, reaching Stage 2 (Top 20) with team GateMasters.
Technologies Used
RISC-VVEGA AS1061SystemVerilogFPGAVision TransformersHardware Acceleration
CategoryFPGA/RTL
TimelineJan 2024
Technologies6