FPGA/RTLPresent
Serial Bus Design
Custom RTL Bus Interconnect with Arbitration & Split Transactions
About This Project
Developing a custom RTL serial bus featuring a fixed-priority arbiter (Master0 > Master1), range-based address decoder, and parameterized master/slave interface modules.
Implemented split-transaction handling with full verification using module-level and top-level testbenches (Verilator + Vivado), and FPGA-ready synthesis flows for both Vivado and Quartus.
Technologies Used
SystemVerilogVerilatorVivadoQuartusRTLArbitration
CategoryFPGA/RTL
TimelinePresent
Technologies6