Serial Bus Design
Custom RTL bus interconnect with priority arbitration and split transactions
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About This Project
Architected a multi-master serial bus system on Intel Cyclone IV FPGA featuring priority arbitration, split transactions, and UART-based inter-FPGA bridge.
The design utilized 1-bit serial data transmission to minimize routing complexity while supporting: • 2 masters and 3 slaves (up to 10KB total memory) • Priority-based arbitration for multi-master coordination • Split transaction protocol for efficient bus utilization • Clock domain crossing via FIFOs for asynchronous operation • UART bridge enabling inter-FPGA communication
Verified through comprehensive RTL verification and successful hardware implementation on Intel Cyclone IV FPGA using Quartus Prime.
Key Features: Low resource utilization, deterministic arbitration, full hardware validation, and modular architecture for scalability.