RV32I Processor Design and Implementation on FPGA

Developed a fully verified 32-bit RV32I processor in SystemVerilog with both single-cycle and pipelined architectures.

Single-Cycle Core: Fully verified RV32I single-cycle CPU with complete instruction support and FPGA-ready architecture.

Pipelined Core: Implemented a 5-stage pipelined RV32I CPU with hazard detection, forwarding, stall control, and branch prediction, achieving full RV32I functional verification.

Skills developed: SystemVerilog, Vivado design flow, RISC-V architecture, pipeline control logic, and hardware verification.