SIMD Processor Array for Convolution Neural Network (Ongoing)

High-Performance CNN Processor with 32-bit ISA on ZedBoard Zynq-7000

Key Features:

• Architected a systolic array accelerator with custom 32-bit ISA, row-stationary dataflow, pipelined processing element design, and hierarchical memory subsystem with PE register files, global buffers, and AXI4 DMA engine for ARM-FPGA communication.

Includes matrix-vector multiplier implementation with UART communication and AXI Stream interfaces.