FPGA/RTL2024

Accumulator with AXI Stream and Output Sum on 7-Segment Display

Digital system with AXI Stream interface for accumulation and 7-segment display

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About This Project

Developed a digital system that reads a stream of numbers via an AXI Stream interface, computes their sum, and displays the result on a pair of 7-segment displays.

Technical Details: • AXI Stream Interface: Implemented handshake protocols to manage input and output data streams • Summation Logic: Used a counter to accurately accumulate the sum • 7-Segment Display Conversion: Designed custom combinational logic • Testbench: Included randomized inputs and assertions for thorough testing

Technologies Used

AXI StreamSystemVerilogXilinx VivadoFPGADigital System Design
CategoryFPGA/RTL
Timeline2024
Technologies5

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