Awarded by
DVCon India 2025
Achievement Details
Category
FPGA/DesignDate Awarded
September 2025
Organization
DVCon India 2025
Achievement Level
Runners-Up
About This Achievement
SLMs on Edge – A lightweight FPGA-based systolic array accelerator and bare-metal inference engine designed to run the full Qwen3 pipeline on the VEGA AT1051 RISC-V SoC.
Key Highlights
- Awarded 1st Runners-up at the DVCon India 2025 Design Contest organized by CDAC Trivandrum
- Designed a custom accelerator for the VEGA AT1051 SoC
- Built a framework capable of running the full Qwen3 inference pipeline on bare metal
- Demonstrated strong hardware–software co-design skills while competing against top university and industry teams
Related Achievements
Impact & Recognition
This achievement demonstrates excellence in fpga/design and represents significant contribution to the field. It showcases innovation, dedication, and the ability to deliver impactful solutions.
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